1. Processed SiIC
2. Optional insulator layer
3. HIII/V layer
4. First electrode structure
5. Light beam area
6. Second electrode structure
7. OD length
8. OD width
9. Insulating distance
10. Second channel
11. First channel
12. HIII/V layer height
13. Insulator height
14. Gap width
15. A/B/C light pulse duration
16. A/B/C time-out interval
17. A/B/C gating duration
18. A/B/C extended duration
19. A/B/C charging duration
20. Carrier energy
21. Gating voltage
22. A/B/C time
23. A/B/C light pulses
24. A/B/C carrier energy levels
25. A/B/C gating curves
26. light intensity
27. Operational value
28. Gating level
1. Field of Invention
The present invention relates to the field of optical detectors grown on processed silicon based circuit structures.
2. Background of the Invention In modern computers the main processing load is handled by a number of silicon based integrated circuits (SiIC""s) Those SiIC""s are placed on boards that provide the electrical interconnections in the form of conductive traces. The boards are electrically connected to each other with connectors and wires.
Due to continuing development, the speed at which the SiIC""s perform their logical operations is consistently rising. At the same time, more and more functions and features are provided by the computer, increasing the number and complexity of specific SiIC""s that are brought into interaction with each other. As a result, the number of wires and traces, as well as their lengths, are also growing. Even though the signal speed outside the SiIC""s is just a fraction of the internal speed, the amount and length of connectors, wires and channels, with their inductance and capacitance, impose a significant limitation on further development of faster SiIC""s.
The logical operations within an SiIC are performed synchronously. For this reason, carefully designed channels have to provide all areas of the IC with clock signals. Distortions of the synchronous clock frequency are known as clock skew, which becomes more and more difficult to handle with increasing frequency and chip size. The clock signals are supplied to the SiIC via a peripheral junction and have to reach each destination over exactly the same distance. As a result, sophisticated channel distribution designs known as H-tree or fan-out designs occupy more and more space of the available SiIC area. In addition, the clock frequencies have reached levels at which local thermal differences affect the resistance and the travel speed of the clocking signal beyond acceptable tolerances. Furthermore, the placement of the clock channels partitions the SiIC and imposes a dimensional limitation on the design of the logical circuitry.
Optical data transmission bypasses the problems imposed by electrical wires and channels. Optical data transmission speed is highly independent of transmission distance and thermal influences. Other advantages include, for instance: no sensitivity to electronic noise, no capacitance or inductance in the transmission paths, no signal interference, vertical accessibility of SiIC""s, and electric decoupling between individual electronic components.
A number of inventions provide for optical data transmission between SiIC""s for data and signal communication as well as for distribution of clock signals. To utilize the advantages provided by optical data transmission to their utmost, it is essential to transform the optical signal into an electric signal as close as possible to the location of the logical operation. The devices that perform the transformation are called optical interconnects (OI""s). They transform a received coherent light beam into a carrier energy with a distinct voltage or vice versa. In the specific form of a metal-semiconductor-metal detector (MSM-detector), the carrier energy is a gating voltage between two metallic electrodes. The conductivity created thereby is in approximate proportion to the intensity or energy of the received light beam. The efficiency of the transformation is defined by the ratio between the energies of the received light beam and that of the generated carrier energy. OI""s can be either emitters or modulators, which convert an electrical signal into an optical signal, or optical detectors (OD), which convert a received optical signal into an electrical signal. A combination of both is also possible, even though the specific and differing tasks emitters and receivers have to perform lead more towards specifically designed and independently performing OD""s.
U.S. Pat. No. 5,537,498 discloses an optical clock distribution system, whereby a bulky OD is brought into close proximity to the location of the logical operation within the SiIC. Conductive channels transmit the converted electrical clock signals from the OD to an electrical subsystem, wherein the clock signal is tuned and distributed over equalized fan-out paths to the final sites of the SiIC. The bulky design of the OD does not allow positioning close to the final destinations of the clock signals, which results in excessive lengths of conductive channels. Consequently, the clock signal has to be additionally tuned, which degrades the advantages achieved by optical clock distribution.
Another invention, disclosed in U.S. Pat. No. 5,568,574, presents modular-based photonic chip-to-chip interconnections for dense three-dimensional multichip module integration. A number of stacked SiIC""s is thereby brought into signal communication by placing OD""s on their opposing surfaces in congruent arrays, such that they can directly exchange optical signals. The OD""s are pre-fabricated and flip chip bonded onto the processed SiIC. They are dimensioned far beyond the sizes required for their operational function in order to have sufficient size for physical placement and the mechanical robustness necessary for the bonding process. As a result, they have an unnecessarily high internal capacitance that has to be charged each time an optical signal is received and converted into an electrical signal. The response time of such an OI is relatively long, and a significant part of the converted electrical energy is consumed to charge the capacitance. Furthermore, the conductive state of an OD such as an MSM-detector fades over an extended time period, which causes the transmitted signal also to fade and to lose its crispness. In summary, the capacitance imposed by the bulky design of the OD degrades the signal coherence such that additional circuitry becomes necessary to compensate for this shortcoming.
Since logical operations are mainly performed within silicon-based IC""s (SiIC""s), there are attempts to also utilize Si-based materials for OD""s. to integrate them together with the logical circuitry. The integration of OD""s and logical circuitry in close proximity reduces the conductive path of the electric signal to the location of the logical operation to a minimum, and the capacitance in the channels is thereby kept at a very low level.
For example, U.S. Pat. No. 5,889,903 discloses a method and apparatus for distributing an optical clock in an integrated circuit. A coherent light beam is split and directed onto several OD""s, which are distributed over the planar structure of an SiIC. The coherent light beam is pulsed with a clock frequency, which is synchronously converted in each of the OD""s into a number of individual electrical clock signals. Hence, all logical circuits of the SiIC operate synchronously, driven by their individually derived clock signal. Unfortunately, the low efficiency of the SiOD""s necessitates the use of amplifiers and buffers, which impose with their capacitance and subsequently with their time delay a latency onto the transmission path between the OI and the clock signal destination, and compromise the overall synchronicity in the SiIC.
Preferred materials for OI""s with a high conversion efficiency are III-V compound materials (III-V) based, for instance, on Gallium-Arsenide (GaAs) or Indium-Gallium-Arsenide (InGaAs). Unfortunately, their integration onto or within processed SiIC""s is problematic. First, because III-V""s have a different crystallographic lattice constant than Si, it is difficult to grow defect-free epitaxial structures. Secondly, the environment to grow III-V layers is highly destructive to a fully processed SiIC: the temperature of the environment is at a level at which metallizations are altered or destroyed, and at which the detailed structure of transistors would be altered substantially during the III-V growth. Oxidized Si also loses its insulating characteristic in the presence of gallium. It is not possible to deposit the III-V compound OI""s at an early stage of the SiIC manufacturing because of specific processing requirements. Once compounds containing gallium have been added to the SiIC, it is undesirable to return the SiIC to the SiIC production sequence, because the gallium may contaminate the SiIC production line.
To bypass and overcome the obstacles described above, sophisticated intermediate fabrication steps could be implemented. However, the whole manufacturing process would become too complex and would not be feasible for industrial fabrication of integrated OI""s.
To avoid these problems, processes known as wire bonding, solder bumping, flip chip bonding or atomic rearrangement are used to bind a pre-manufactured GaAs- or InGaAs-OI onto a processed SiIC. The physical manipulation and the binding processes required for this imply disadvantageous dimensioning of the OI as described in U.S. Pat. No. 5,568,574. III-V materials are usually grown on III-V substrates, but such substrates have different thermal expansion coefficients from silicon, which makes bonding of large III-V and Si substrates difficult, and specifically makes precise bonding difficult. Techniques such as wire bonding, flip chip bonding, and solder bumping also require significantly large dimensions or lengths of bonds, which increase both capacitance and inductance and reduce the performance.
Therefore, there exists a need to provide OI""s from III-V compound materials deposited directly on a fully processed SiIC. The current invention addresses this problem.
One shortcoming of optical data transmission is the attenuation in the optical transmission path, which can vary due to aging processes or hazardous operational conditions. It is also dependent, for example, on the transmission length, the number of connectors, and the transmission media.
Therefore, there also exists a need for reliable optical signal transmission that is independent of intensity discrepancies of light beams received within an OD. The current invention addresses this problem also.
Accordingly, it is a primary object of the present invention to place an OD in close proximity to the location of a logical operation within a SiIC.
It is a further object of the present invention to provide an OD with a minimal internal capacitance.
It is a further object of the present invention to provide an OD with a high efficiency.
It is yet another object of the present invention to provide an OD device unaffected by intensity fluctuations of the received optical signal.
The above objects and advantages, as well as numerous improvements attained by the apparatus and method of the invention, are pointed out below.
III-V compounds can be deposited at temperatures around 250 degrees Centigrade instead of the usual 600 to 700 degrees. This so-called low temperature process has been utilized to grow GaAs, for instance as buffer layers on a GaAs substrate. Layers deposited at those low temperatures have an excess concentration of As (or the group V element) as well as a high concentration of growth defects which render the crystalline structure highly heterogeneous. The advantage of the low temperature growth is that it can be performed on fully processed SiIC""s without risking their destruction.
The present invention provides an optical switching device grown on a fully processed circuit structure, preferably made from silicon-based material. The device has the following layers: a template layer, preferably electrically insulating, on the circuit structure; a heterogeneous crystalline layer grown on top of the template layer at a low temperature (200-250xc2x0 C.) ; and at least one top layer with a number of electrode areas and deposited on the crystalline layer. The top layer preferably has a predetermined refractive index. The template layer may be deposited on the processed circuit, or the circuit may be selectively etched to form the template layer.
The heterogeneous crystalline layer may be a GaAs, InGaAs, or InGaNAs material. It preferably has a predetermined electrical resistance, and receiving a light beam can reduce the resistance to initiate a temporary conductivity in the layer for a distinct conduction duration. During the conduction duration, the device has a capacitance with a distinct charging duration from a current flowing between the electrode areas. Preferably, the charging duration is shorter than or equal to the conduction duration.
The device may also have an additional layer above or below the heterogeneous crystalline layer. The additional layer has a wider bandgap than the heterogeneous crystalline layer, and therefore provides electron and hole confinement and passivation to surface and interface recombination.
An epitaxially grown III-V compound material(III-V) has a highly absorbing characteristic for light at wavelengths desirable for optical interconnects. Hence, the received light beam can be absorbed relatively completely, even within a thin layer of III-V material, efficiently generating electrons and holes, or charge carriers. The carriers are able to travel to establish a conductive state between adjacent electrodes and perform thereby the switching function of the OD. When a traveling carrier hits a defect or impurity it can recombine. Defects and impurities are numerous in heterogeneous crystalline III-V (hIII/V) compound structures, such that the average lifetime of carriers generated in layer is very short. The efficiency of light beams with a duration as presently utilized for known OD""s would be therefore too low in hIII/V layers.
Lasers when modelocked produce pulsed light beams with a duration that is a fraction of that in conventional OD""s. Such pulses can effectively be modulated to carry information using high speed mirroring devices such as reflective quantum well modulators. The modulators and the associated electrical drive signals only have to operate at the repetition rate of the pulses, not at the short time scales of the pulse duration, to allow different information to be carried on each pulse.
This possibility is utilized in the current invention to create an OD for coherent light beams with a duration that is shorter than the average lifetime of the carriers within a hIII/V layer. The thereby generated carrier pulses are short in duration and sum to low numbers of carriers. The structure is, in a preferred embodiment, designed so that the generated carriers are substantially transported to the electrodes in a time shorter than or comparable to the average lifetime of the carriers within a hIII/V layer. Thus, the carriers are able to discharge the device capacitance efficiently before they would otherwise have recombined, and the short lifetime of the generated carriers does not substantially prevent an OD that is efficient. The short recombination time of the carriers ensures also that the device is very fast, being ready rapidly to receive another pulse of information. The discharging of the device capacitance creates a voltage electrical signal as required for the optical interconnect operation.
The device described above is made by depositing a template layer on a processed semiconductor, growing a heterogeneous crystalline layer of III-V compound related material on the template in a low temperature growing environment, and depositing a number of electrical and optical operating layers on top of the III-V compound related material. An additional step of annealing the device at a temperature of between 250 and 400xc2x0 C. for a short time period may occur after the layer is grown.
The invention is used to provide signals from single pulsed light beams either for data transmission or as clock signals.
The present invention also provides a method for converting a pulsed light beam with a minimum pulse duration into an electrical switching signal with a switching duration that is at least equal to the pulse duration. The method has the following steps: pulsing the light beam; directing the light beam into the heterogeneous crystalline layer structure described above, thereby altering the conductivity of the layer and initiating a current flow between electrodes deposited on the layer; charging a capacitance of the structure; and transmitting the current flow between the electrodes to a gate terminal of a transistor that is conductively connected to at least one of the electrodes.
The present invention also provides a converting device incorporating the optical switching device described above.
The converting device converts a number of periodically alternating intensity differences of first and second light beams into a number of digital electrical signals with two predetermined voltage values, corresponding to the two logical values of a bit: a xe2x80x9c1xe2x80x9d and a xe2x80x9c0xe2x80x9d. The converting device includes: first and second optical switching devices (or optical interconnects (OI""s)) for receiving first and second light beams, respectively; a positive voltage supply channel connected to a first primary electrode of the first OI and to a first primary terminal of an n-switched transistor (preferably PMOS); a negative voltage supply channel connected to a second primary electrode of the second OI and to a second primary terminal of a p-switched transistor (preferably NMOS); a central node connected to a first secondary electrode of the first OI, to a second secondary electrode of the second OI, to a first gate of the p-switched transistor, and to a second gate of the n-switched transistor; and an output channel connected to a first secondary terminal of the p-switched transistor and a second secondary terminal of the n-switched transistor. The converting device is used for differential signal processing of the two light beams. The two received beams have complementary intensities that are converted into an electrical signal with a poling value that corresponds to the difference between the two intensities. Preferably, the electrical signal has a voltage level that depends on the two intensities. Depending on the poling value, the output channel is connected with either a positive or negative source voltage.